4단계 BK21 미래국방 지능형ICT 교육연구단

IEEE TRANSACTIONS ON ELECTRON DEVICES

200-mm Si CMOS Process-Compatible 

Integrated Passive Device Stack for Millimeter-

Wave Monolithic 3-D Integration

Minsik Park , Jonghyun Song, Jaeyong Jeong, Jeong-Taek Lim, Jae-Hyeok Song, Won-Chul Lee, Gapseop Sim, Huijae Cho, Dongeun Yoo, Minho Kang, Hyoungho Ko, Jooseok Lee, Kyounghoon Yang, Choul-Young Kim, Youngsu Kim, Woo-Suk Sul, Sanghyeon Kim, Jongwon Lee

Abstract

 In this article, we have demonstrated a simple 200-mm Si CMOS process-based integrated passive device (IPD) stack for millimeter-wave (mmW) monolithic 3-D (M3D) integration. By developing a double chemical mechanical polishing (CMP) technique for the final intermetal dielectric (IMD) process, an rms value of less than 1 nm for the topsurface roughness of the IPD stack was achieved, resulting in uniform 3-D integration of a 100-nm-thick active layer of the InGaAs high-electron-mobility transistor (HEMT) on the stack. The stack included a trap-rich layer (TRL) and a buried oxide layer (BOX) with a high-resistance Si substrate (HRS) to achieve high-frequency properties. The TRL and BOX were optimized to keep wafer bowing as low as possible while minimizing the radio frequency (RF) loss. A fabricated coplanar waveguide (CPW) based on a TRL with poly-Si deposited by low-pressure chemical vapor deposition (LP-CVD) and a BOX with SiO2 deposited by LP-CVD exhibited an insertion loss (IL) value of 0.77 dB/mm at 40 GHz. IL values of the developed CPW were comparable to those of CMOS foundries, despite using thinner metal thickness, under a condition of the same metal width. The fabricated passive devices showed good quality factor (Q) characteristics sufficient to be utilized up to the V-band. In particular, the maximum Q values of the inductors are the best among Si lumped inductors reported in the mmW bands to date.

https://ieeexplore.ieee.org/document/10219560